This invention relates to a logic circuit and, more particularly, to a logic circuit that may be used as an address inverter.
An address inverter is for producing, in response to an address signal variable between a low and a high level, such as a logic "1" and a logic "0" level, a first and a second output signal that vary with phases opposite to and same as the address signal, respectively. The address inverters are used in combination with a plurality of decoders, each connected to the address inverters, in an I.C. memory in order to decode various address signals from time to time. As will later be described in detail with reference to a few figures of the accompanying drawing, a conventional address inverter produces the output signals with levels thereof rendered lower than a predetermined level during an interval of time in which the address signal varies from a first level to a second between the low and the high levels. Such output signals will make the decoders having a threshold level equal to the predetermined level erroneously decode each address signal into two or more decoder output signals.